// `include "calc_phase.v"
`default_nettype none

module tb_calc_phase;
reg          clk    ;
reg          rst_n  ;
reg          vld_in ;
reg  [15:0]  x      ;
reg  [15:0]  y      ;
wire         vld_out;
wire [15:0]  p      ;

calc_phase u_calc_phase(
  .clk     (clk     ),
  .rst_n   (rst_n   ),
  .vld_in  (vld_in  ),
  .x       (x       ),
  .y       (y       ),
  .vld_out (vld_out ),
  .p       (p       )
);


localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
  $dumpfile("sim/build/tb_calc_phase.vcd");
  $dumpvars(0, tb_calc_phase);
end

initial begin
  #1 rst_n<=1'bx;clk<=1'bx;
  #(CLK_PERIOD*3) rst_n<=1;
  #(CLK_PERIOD*3) rst_n<=0;clk<=0;
  repeat(5) @(posedge clk);

  rst_n<=1;
  vld_in<=1;
  x<=10;
  y<=10;
  repeat(17) @(posedge clk);
  x<=-3;
  y<=4;
  repeat(17) @(posedge clk);
  x<=3;
  y<=-4;
  repeat(17) @(posedge clk);
  x<=-10;
  y<=0;
  repeat(17) @(posedge clk);
  $finish(2);
end

endmodule
`default_nettype wire